Via Wireless Systems
VWS-SDR44
Via SDR M44
Dual-radio 4x4 MIMO SDR for edge compute and wireless OEMs.
Works with
- NVIDIA Jetson
- Embedded Edge AI
- Mesh System
- Industrial PCs
- x86 / AMD edge NUCs
- Robotics compute
- Private wireless R&D
- Custom M.2 carriers
- Software-defined radio
The module
Dual-radio SDR for edge compute platforms
M.2 Key-M module with two AD9361 radios and an Artix UltraScale+ FPGA. Supports TDD 4x4 or FDD 2x2 for edge hosts, private wireless, and custom RF backends.
AI robotics
Give robots and fleets a longer-range link than Wi-Fi, with bands you can tune for the job.
Edge compute
Fits M.2 hosts and industrial PCs that need a tunable dual-radio SDR.
Mesh systems
Dual-radio MIMO radio front end for multi-hop mesh, with the PHY running on the FPGA.
Wireless OEMs
Add a dual-radio MIMO front end to your product and keep PHY control on the FPGA.
Specifications
What Via SDR M44 brings to your platform
Wideband dual-radio hardware in an M.2 slot for edge boxes, robots, and wireless products that need a custom RF stack on the host.
70 MHz to 6 GHz
Tunable RF coverage
Up to 56 MHz
Channel bandwidth
4x4 TDD
MIMO spatial paths
PCIe Gen3 x4
Host throughput
RF
- Transceivers
- Two Analog Devices AD9361 radios (independent)
- Frequency range
- 70 MHz to 6 GHz (AD9361)
- Channel bandwidth
- 200 kHz to 56 MHz
- MIMO modes
- TDD 4x4, FDD 2x2, or host-only 2x2 (one radio)
- Antenna ports
- 4x MHF4 (U.FL compatible)
- Front-end
- Per-port T/R switching, TX bias, RX protection
Compute & host
- FPGA
- AMD Artix UltraScale+ XCAU10P
- Form factor
- M.2 Key-M (3080)
- Host
- PCIe Gen3 x4
- On-module processing
- PHY, packet path, and accelerators can run on the FPGA with full dual-radio control
Timing & sync
- Reference
- Shared 38.4 MHz TCXO to both radios and the FPGA
- Multi-chip sync
- MCS path for coordinated dual-radio operation
Power
- Host power
- 3.3 V from the M.2 connector
- 4x4 TDD
- AUX 12 V needed for full four-path TDD
- Part number
- VWS-SDR44
Gallery